Arrow Lake (microprocessor)

Arrow Lake

Launched	October 24, 2024 (2024-October-24)
Designed by	Intel
Manufactured by	Intel TSMC
Fabrication process	TSMC N3B TSMC N5P TSMC N6
Codename(s)	ARL
Platform(s)	Desktop Mobile
Branding
Brand name(s)	Core Ultra
Generation	Series 2
Socket(s)	LGA 1851 BGA 2114[1]
Instructions & Architecture
Instructions set	x86
Instructions	x86-64
P-core architecture	Lion Cove
E-core architecture	Skymont
Cores
Peak core clock	Up to 5.7 GHz
P-core L1 cache	112 KB (per core): 64 KB instructions 48 KB data
E-core L1 cache	96 KB (per cluster): 64 KB instructions 32 KB data
P-core L2 cache	3 MB (per core)
E-core L2 cache	4 MB (per cluster)
P-core L3 cache	3 MB (per core)
E-core L3 cache	3 MB (per cluster)
Graphics
Graphics architecture	Xe-LPG Xe-LPG+
Execution Units	Up to 64 EUs
Xe Cores	Up to 8 Xe Cores
Peak graphics clock	2.0 GHz
NPU
Architecture	NPU 3720
TOPS	13
Memory Support
Type	DDR5-6400
Memory channels	2 channels
Maximum capacity	192 GB
I/O
PCIe support	PCIe 5.0
PCIe lanes	20 PCIe 5.0 lanes 4 PCIe 4.0 lanes
DMI version	DMI 4.0 x8
History
Predecessor	Meteor Lake
Variant	Lunar Lake
Successor	Panther Lake

Arrow Lake is the codename for Core Ultra Series 2 processors designed by Intel, released on October 24, 2024. It follows on from Meteor Lake which saw Intel move from monolithic silicon to a disaggregated MCM design. Meteor Lake was limited to a mobile release while Arrow Lake includes both socketable deskop processors and mainstream and enthusiast mobile processors. Core Ultra 200H and 200HX series mobile processors will follow in early 2025.^[2]

The first official mention of Arrow Lake came on February 17, 2022 at Intel's Investor Meeting where it was confirmed that Arrow Lake would be the successor to Meteor Lake. Arrow Lake was confirmed to use a disaggregated construction and would be fabricated on Intel's 20A node and external nodes.^[3]

In September 2023, Intel CEO Pat Gelsinger showcased a 20A wafer at Intel's Innovation event containing Arrow Lake test dies, reiterating that Arrow Lake products were on schedule.^[4] On December 14, 2023, Meteor Lake launched in 9W and 15W form factors for ultra thin notebooks.^[5]

At CES in January 2024, Intel stated that Arrow Lake would launch for desktop in the second half of 2024.^[6] Intel claimed that Arrow Lake would be the "world's first gaming processor with an AI accelerator" despite AMD's Ryzen 8000G desktop APUs, codenamed "Phoenix-G", with a dedicated XDNA AI engine launching first in January 2024.^[7] On May 20, 2024, Intel reaffirmed that Arrow Lake was on track for a Q4 2024 release with an update promised at Computex in the following weeks. On June 4, 2024, Intel shared details on the Lion Cove P-cores and Skymont E-core architectures that are shared between Arrow Lake and Lunar Lake.

Arrow Lake-S desktop processors were announced on October 10, 2024 with an October 24 release date.^[8]

Arrow Lake is a two-way x86 architecture designed to scale from 28W mobile form factors to 125W enthusiast desktop segments. The architectural construction behind Arrow Lake maintains many of the direct elements from Meteor Lake. It is a disaggregated MCM design fabricated on various nodes from TSMC. Arrow Lake reuses the same SoC and I/O extender tiles from Meteor Lake while adding a new compute tile and a smaller graphics tile intended for desktop.

Tile	Node	EUV	Die size	Ref.
Compute tile	TSMC N3B		114.5 mm2	[9]
Graphics tile	TSMC N5P		Un­known
SoC tile	TSMC N6		Un­known
I/O extender tile	TSMC N6		Un­known
Foveros interposer base tile	Intel 16 (22FFL)		300.9 mm2

The previous generation Meteor Lake used the Intel 4 process on its compute tile with Arrow Lake originally planning to move to Intel's 20A node. In September 2024, Intel announced the cancellation of its 20A node so it could shift its focus to the development of 18A instead. Intel's 20A node planned to introduce gate-all-around (GAA) transistors, which Intel refers to as RibbonFET, and those transistors receive backside power delivery that Intel calls PowerVia. RibbonFET is Intel's first new transistor design since the introduction of FinFET in 2011.^[10] Arrow Lake's compute tile is fabricated on TSMC's N3B node instead of 20A.^[11] Similar to what the previous generation Meteor Lake did, Arrow Lake's compute tile introduces both new Lion Cove P-cores and new Skymont E-cores. Arrow Lake's Lion Cove and Skymont core architectures are also shared with Lunar Lake.

Lion Cove P-cores features wider decoder and dispatch engines, a greater number of integers ALUs, larger L2 caches, and a redesigned cache hierarchy. Intel claims a 9% IPC uplift for Arrow Lake's Lion Cove cores.^[12] Lion Cove in Arrow Lake has an increased 3 MB of L2 cach compared to 2.5 MB in Lunar Lake's Lion Cove implementation. Lion Cove's L2 cache is 50% larger over the previous generation Raptor Cove core with 2 MB of L2 cache. Lion Cove has an L2 bandwidth of 32 bytes per cycle.^[13] Lion Cove P-cores include support for AVX-512 instructions but AVX-512 has been disabled in Arrow Lake processors due to its heterogenous architecture. The Skymont E-cores do not feature AVX-512 instructions support so AVX-512 is disabled to ensure that both core types are equal in their capabilities.

There has been a clock speed regression for Lion Cove P-cores in Arrow Lake-S desktop processors.^[14] The Core Ultra 9 285K has a peak clock speed of 5.7 GHz compared to the higher 6.2 GHz clock speed of the Raptor Lake Core i9-14900KS.^[15]

Simultaneous multithreading (SMT) has been removed from Arrow Lake's Lion Cove P-cores.^[16] SMT first made its debut in an Intel desktop processor with the Northwood-based Pentium 4 in November 2002. Its removal in Arrow Lake marks the first time since then that SMT has been completely removed from a new x86-64 Intel performance-oriented core architecture rather than it simply being disabled in some lower-end Celeron and Pentium SKUs.^[a] SMT, or Intel's marketing term HyperThreading, allows a single physical CPU core with 2 threads to execute two tasks simultaneously. In the early 2000s, SMT was a way to add more processing threads to dual and quad-core CPUs while not using too much die space. The removal of SMT allows the physical core die area to be reduced. Increasing the number of processing threads with a greater number of physical cores can compensate for the removal of SMT providing 2 threads per core.^[17] Many ARM-based processors, such as Apple's M series SoCs, do not feature SMT as it is less beneficial on processors with a short processor pipeline and including it increases the physical core area. With a longer processor pipeline, like the one used by Intel, it is more difficult to keep the CPU cores fed with useful data in a workload. Cores with longer pipelines are able to support high clock speeds but with fewer instructions per clock (IPC).^[17]

Skymont E-cores focus on enhanced branch prediction and instruction fetch, increased throughput for 128-bit floating point and SIMD vector data types, and their L2 cache receiving a doubling in bandwidth. Intel claims a 32% IPC uplift in multi-threaded integer workloads compared to Gracemont and 55% in multi-threaded floating point.^[18]

The physical layout of P-cores and E-cores has changed in Arrow Lake with a cluster of four E-cores placed between two P-cores.^[19] In contrast, Alder Lake, Raptor Lake, and Meteor Lake placed all P-cores together in one group and all E-cores together in another. The benefit of placing E-cores inbetween P-cores is it reduces core-to-core latency when moving instructions or data between the P-cores and E-cores. The previous approach required data to travel a longer distance along the ring bus between both core types.

Arrow Lake's graphics tile remains largely unchanged architecturally from Meteor Lake. Just like Meteor Lake, the graphics tile in Arrow Lake is fabricated on TSMC's N5P node.^[20] Arrow Lake-S desktop processors feature 4 X^e-LPG cores based on the Alchemist graphics architecture. However, Arrow Lake mobile processors feature up to 8 slightly modified X^e-LPG+ (Gen12.74) cores which add support for Dot Product Accumulate Systolic (DPAS) instructions. DPAS instructions were included in X^e-HPG cores for discrete Arc graphics but were disabled in the lower power X^e-LPG variant. DPAS instructions allow FP16, BF16 and INT4 data types to be multiplied, giving the GPU the ability to perform more operations per cycle.

Arrow Lake reuses the same SoC tile design from Meteor Lake, fabricated on TSMC's N6 node. The SoC tile used for Arrow Lake-S desktop processors was originally designed for cancelled Meteor Lake-S processors for desktop. It does not contain any low power E-cores. Mobile variants of Arrow Lake reuse Meteor Lake's SoC tile that includes two Crestmont low-power E-cores, which are different to the Skymont E-cores in the CPU compute tile. The Crestmont low-power E-cores do not have an L3 cache like the Skymont E-cores do in the CPU tile.

Arrow Lake uses the same Neural Processing Unit (NPU) as found in Meteor Lake that provides 13 TOPS of INT8 rather than the 45 TOPS NPU 4 found in Lunar Lake. For comparison, Ryzen 8000 desktop processors have an NPU capable of 39 TOPS.^[21]

Arrow Lake is Intel's first desktop architecture to feature DDR5 memory support exclusively with support for DDR4 being removed. Alder Lake and Raptor Lake supported both DDR4 and DDR5 memory. Arrow Lake-S desktop processors support the same DDR5-5600 UDIMM speeds as Raptor Lake but Arrow Lake has added support for Clock Unbuffered DIMM (CUDIMM) and Clock Short Outline DIMM (CSODIMM) memory. CUDIMMs add a clock driver to traditional unbuffered DIMMs that is able to regenerate the clock signal locally on the DIMM for better stability at high memory speeds.^[22] With CUDIMMs and motherboard support, Arrow Lake is able to run overclocked DDR5-10000.^[23] At Computex in June 2024, ASRock showed a LGA 1851 socket motherboard with CAMM2 memory slots.^[24]

Arrow Lake-S officially supported DDR5 speeds

		Memory clock (MT/s)
		1DPC	2DPC
UDIMM	1R	5600	4800
	2R		4400
SODIMM	1R	5600	5600
	2R
CUDIMM	1R	6400	4800
	2R		4400
CSODIMM	1R	6400
	2R

Branding	SKU	Cores (threads)		Clock rate (GHz)				Arc Graphics		NPU (TOPS)	Cache		Power		Released	Price (USD)[i]
				Base		Turbo
		P	E	P	E	P	E	Xe Cores (XVEs)	Clock (GHz)		L2	L3	Base	Turbo
Core Ultra 9	285K	8 (8)	16 (16)	3.7	3.2	5.7	4.6	4 (64)	2.0	13	40 MB	36 MB	125 W	250 W	Oct 24, 2024	$589
Core Ultra 7	265K		12 (12)	3.9	3.3	5.5	4.6	4 (64)	2.0		36 MB	33 MB	125 W	250 W		$394
	265KF							—								$379
Core Ultra 5	245K	6 (6)	8 (8)	4.2	3.6	5.2	4.6	4 (64)	1.9		26 MB	24 MB	125 W	159 W		$309
	245KF							—								$294