Wikipedia

SONOS

For other uses, see Sonos (disambiguation).

SONOS, short for "silicon–oxide–nitride–oxide–silicon", more precisely, "polycrystalline silicon"—"silicon dioxide"—"silicon nitride"—"silicon dioxide"—"silicon",[1]: 121  is a cross sectional structure of MOSFET (metal–oxide–semiconductor field-effect transistor), realized by P.C.Y. Chen of Fairchild Camera and Instrument in 1977.[2] This structure is often used for non-volatile memories, such as EEPROM and flash memories. It is sometimes used for TFT LCD displays.[3] It is one of CTF (charge trap flash) variants. It is distinguished from traditional non-volatile memory structures by the use of silicon nitride (Si3N4 or Si9N10) instead of "polysilicon-based FG (floating-gate)" for the charge storage material.[4]: Fig. 1  A further variant is "SHINOS" ("silicon"—"hi-k"—"nitride"—"oxide"—"silicon"), which is substituted top oxide layer with high-κ material. Another advanced variant is "MONOS" ("metal–oxide–nitride–oxide–silicon").[5]: 137 [6]: 66  Companies offering SONOS-based products include Cypress Semiconductor, Macronix, Toshiba, United Microelectronics Corporation and Floadia Archived 2022-11-01 at the Wayback Machine.

Description

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Cross sectional drawing of a SONOS memory cell

A SONOS memory cell is formed from a standard polysilicon N-channel MOSFET transistor with the addition of a small sliver of silicon nitride inserted inside the transistor's gate oxide. The sliver of nitride is non-conductive but contains a large number of charge trapping sites able to hold an electrostatic charge. The nitride layer is electrically isolated from the surrounding transistor, although charges stored on the nitride directly affect the conductivity of the underlying transistor channel. The oxide/nitride sandwich typically consists of a 2 nm thick oxide lower layer, a 5 nm thick silicon nitride middle layer, and a 5–10 nm oxide upper layer.

When the polysilicon control gate is biased positively, electrons from the transistor source and drain regions tunnel through the oxide layer and get trapped in the silicon nitride. This results in an energy barrier between the drain and the source, raising the threshold voltage Vt (the gate-source voltage necessary for current to flow through the transistor). The electrons can be removed again by applying a negative bias on the control gate.

A SONOS memory array is constructed by fabricating a grid of SONOS transistors which are connected by horizontal and vertical control lines (wordlines and bitlines) to peripheral circuitry such as address decoders and sense amplifiers. After storing or erasing the cell, the controller can measure the state of the cell by passing a small voltage across the source-drain nodes; if current flows the cell must be in the "no trapped electrons" state, which is considered a logical "1". If no current is seen the cell must be in the "trapped electrons" state, which is considered as "0" state. The needed voltages are normally about 2 V for the erased state, and around 4.5 V for the programmed state.

Comparison with Floating-Gate structure

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Generally SONOS is very similar to traditional FG (floating gate) type memory cell,[1]: 117  but hypothetically offers higher quality storage. This is due to the smooth homogeneity of the Si3N4 film compared with polycrystalline film which has tiny irregularities. Flash requires the construction of a very high-performance insulating barrier on the gate leads of its transistors, often requiring as many as nine different steps, whereas the oxide layering in SONOS can be more easily produced on existing lines and more easily combined with CMOS logic.

Additionally, traditional flash is less tolerant of oxide defects[citation needed] because a single shorting defect will discharge the entire polysilicon floating gate. The nitride in the SONOS structure is non-conductive, so a short only disturbs a localized patch of charge. Even with the introduction of new insulator technologies this has a definite "lower limit" around 7 to 12 nm, which means it is difficult for flash devices to scale smaller than about 45 nm linewidths. But, Intel-Micron group have realized 16 nm planar flash memory with traditional FG technology.[7]: 13 [8] SONOS, on the other hand, requires a very thin layer of insulator in order to work, making the gate area smaller than flash. This allows SONOS to scale to smaller linewidth, with recent examples being produced on 40 nm fabs and claims that it will scale to 20 nm.[9] The linewidth is directly related to the overall storage of the resulting device, and indirectly related to the cost; in theory, SONOS' better scalability will result in higher capacity devices at lower costs.

Additionally, the voltage needed to bias the gate during writing is much smaller than in traditional flash. In order to write flash, a high voltage is first built up in a separate circuit known as a charge pump, which increases the input voltage to between 9 V to 20 V. This process takes some time, meaning that writing to a flash cell is much slower than reading, often between 100 and 1000 times slower. The pulse of high power also degrades the cells slightly, meaning that flash devices can only be written to between 10,000 and 100,000 times, depending on the type. SONOS devices require much lower write voltages, typically 5–8 V, and do not degrade in the same way. SONOS does suffer from the converse problem however, where electrons become strongly trapped in the ONO layer and cannot be removed again. Over long usage this can eventually lead to enough trapped electrons to permanently set the cell to the "0" state, similar to the problems in flash. However,[citation needed] in SONOS this requires on the order of a 100 thousands write/erase cycles,[10] 10 to 100 times worse compared with legacy FG memory cell.[11]

History

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Background

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Further information: Metal–nitride–oxide–semiconductor transistor

In 1957, Frosch and Derick were able to manufacture the first silicon dioxide field effect transistors at Bell Labs, the first transistors in which drain and source were adjacent at the surface.[12] Subsequently, Dawon Kahng led a paper demonstrating a working MOSFET with their Bell Labs team in 1960. Their team included E. E. LaBate and E. I. Povilonis who fabricated the device; M. O. Thurston, L. A. D’Asaro, and J. R. Ligenza who developed the diffusion processes, and H. K. Gummel and R. Lindner who characterized the device.[13][14]

Later, Kahng went on to invent the floating-gate MOSFET with Simon Min Sze at Bell Labs, and they proposed its use as a floating-gate (FG) memory cell, in 1967.[15] This was the first form of non-volatile memory based on the injection and storage of charges in a floating-gate MOSFET,[16] which later became the basis for EPROM (erasable PROM), EEPROM (electrically erasable PROM) and flash memory technologies.[17]

Charge trapping at the time was an issue in MNOS transistors, but John Szedon and Ting L. Chu revealed in June 1967 that this difficulty could be harnessed to produce a nonvolatile memory cell. Subsequently, in late 1967, a Sperry research team led by H.A. Richard Wegener invented the metal–nitride–oxide–semiconductor transistor (MNOS transistor),[18] a type of MOSFET in which the oxide layer is replaced by a double layer of nitride and oxide.[19] Nitride was used as a trapping layer instead of a floating gate, but its use was limited as it was considered inferior to a floating gate.[20] Charge trap (CT) memory was introduced with MNOS devices in the late 1960s. It had a device structure and operating principles similar to floating-gate (FG) memory, but the main difference is that the charges are stored in a conducting material (typically a doped polysilicon layer) in FG memory, whereas CT memory stored charges in localized traps within a dielectric layer (typically made of silicon nitride).[16]

Development

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SONOS was first conceptualized in the 1960s. MONOS is realized in 1968 by Westinghouse Electric Corporation.[21][22] In the early 1970s initial commercial devices were realized using PMOS transistors and a metal-nitride-oxide (MNOS) stack with a 45 nm nitride storage layer. These devices required up to 30V to operate. In 1977, P.C.Y. Chen of Fairchild Camera and Instrument introduced a SONOS cross sectional structured MOSFET with tunnel silicon dioxide of 30 Ångström thickness for EEPROM.[2] According to NCR Corporation's patent application in 1980, SONOS structure required +25 volts and −25 volts for writing and erasing, respectively.[23] It was improved to +12 V by PMOS-based MNOS (metal-nitride-oxide-semiconductor) structure.[24]

By the early 1980s, polysilicon NMOS-based structures were in use with operating voltages under 20 V. By the late 1980s and early 1990s PMOS SONOS structures were demonstrating program/erase voltages in the range of 5–12 volts.[25] On the other hand, in 1980, Intel realized highly reliable EEPROM with double layered polysilicon structure, which is named FLOTOX,[26] both for erase and write cycling endurance and for data retention term.[27] SONOS has been in the past produced by Philips Semiconductors, Spansion, Qimonda and Saifun Semiconductors.

Recent efforts

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In 2002, AMD and Fujitsu, formed as Spansion in 2003 and later merged with Cypress Semiconductor in 2014, developed a SONOS-like MirrorBit technology based on the license from Saifun Semiconductors, Ltd.'s NROM technology.[28][29][30] As of 2011 Cypress Semiconductor developed SONOS memories for multiple processes,[31] and started to sell them as IP to embed in other devices.[32] UMC has already used SONOS since 2006 [33] and has licensed Cypress for 40 nm[34] and other nodes. Shanghai Huali Microelectronics Corporation (HLMC) has also announced[35] to be producing Cypress SONOS at 40 nm and 55 nm.

In 2006, Toshiba developed a new double tunneling layer technology with SONOS structure, which utilize Si9N10 silicon nitride.[36][37] Toshiba also researches MONOS ("Metal-Oxide-Nitride-Oxide-Silicon") structure for their 20 nm node NAND gate type flash memories.[38] Renesas Electronics uses MONOS structure in 40 nm node era.[39][40]: 5  which is the result of collaboration with TSMC.[41]

While other companies still use FG (floating gate) structure.[42]: 50  For example, GlobalFoundries use floating-gate-based split-gate SuperFlash ESF3 cell for their 40 nm products.[43] Some new structure for FG (floating gate) type flash memories are still intensively studied.[44] In 2016, GlobalFoundries developed FG-based 2.5V Embedded flash macro.[45] In 2017, Fujitsu announced to license FG-based ESF3/FLOTOX structure,[26][27] which is originally developed by Intel in 1980, from Silicon Storage Technology for their embedded non-volatile memory solutions.[46][47][48] As of 2016, Intel-Micron group have disclosed that they stayed traditional FG technology in their 3-dimensional NAND flash memory.[7] They also use FG technology for 16 nm planar NAND flash.[8]

See also

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References

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  1. ^ a b Micheloni, Rino; Crippa, Luca; Marelli, Alessia (2010). Inside NAND Flash Memories (Google Books). Springer Science & Business Media. ISBN 9789048194315.
  2. ^ a b Chen, P. C. Y. (1977). "Threshold-alterable Si-gate MOS devices". IEEE Transactions on Electron Devices. 24 (5): 584–586. Bibcode:1977ITED...24..584C. doi:10.1109/T-ED.1977.18783. ISSN 0018-9383. S2CID 25586393.
  3. ^ Chen, S. C.; Chang, T. C.; Liu, P. T.; Wu, Y. C.; Lin, P. S.; Tseng, B. H.; Shy, J. H.; Sze, S. M.; Chang, C. Y.; Lien, C. H. (2007). "A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory". IEEE Electron Device Letters. 28 (9): 809–811. Bibcode:2007IEDL...28..809C. doi:10.1109/LED.2007.903885. ISSN 0741-3106. S2CID 40413991.
  4. ^ Lee, M. C.; Wong, H. Y. (2013). "Charge Loss Mechanisms of Nitride-Based Charge Trap Flash Memory Devices". IEEE Transactions on Electron Devices. 60 (10): 3256–3264. Bibcode:2013ITED...60.3256L. doi:10.1109/TED.2013.2279410. ISSN 0018-9383. S2CID 41506023.
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  7. ^ a b "NAND Flash Memory Roadmap" (PDF). TechInsights Inc. June 2016. Archived from the original (PDF) on 2018-06-25. Retrieved 2018-03-23.
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    The Intel 2816 uses the FLOTOX structure, which has been discussed in detail in the literaturel. Basically, it utilizes an oxide of less than 200A thick between the floating polysilicon gate and the N+ region as shown in Figure 1.
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  34. ^ Cypress Press Release, 21 Jan 2015
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